Workshop: Workshop of Graph Neural Networks and Systems (GNNSys'21)

Keynote Talk: Graph Representation Learning for Chip Design by Azalia Mirhoseini (Google)

[ Abstract ]
Fri 9 Apr 8:50 a.m. PDT — 9:20 a.m. PDT


Many core problems in systems and hardware design are combinatorial optimization or decision making tasks on graph structured data. Examples of such problems are compiler optimization, physical design, or design verification, where the programs or hardware are described in graph formats. These computational graphs pose new challenges to ML-based algorithms since their state and action spaces are orders of magnitude larger than common AI benchmarks in robotics and games. In this talk, I will go over some of our research on tackling optimization problems on graph data and present our recent work on optimizing chip floorplanning with reinforcement learning. Our approach has the ability to learn from past experience and improve over time. The optimization relies on a new edge-based graph convolution model that captures the properties of the chip description graph and the placement policy can generalize to unseen blocks. Our objective is to minimize PPA (power, performance, and area), and we show that, in under 6 hours, our method can generate placements that are superhuman or comparable on modern accelerator chips, whereas existing baselines require human experts in the loop and can take several weeks.